The present invention generally relates to complementary metal-oxide-semiconductor (CMOS) fabrication methods and related structures. More specifically, the present invention relates to methods and device architectures for fabricating vertical field-effect transistor (VFET) devices with symmetric and asymmetric source/drain regions.
In contemporary CMOS device fabrication processes, the design of top and bottom source/drain regions is a factor in the performance characteristics of a VFET device. Known VFET fabrication methods, including epitaxial grown processes, employ complicated processes requiring several detailed steps and specialized functions in order to fabricate devices using vertical fin structures.